Dane Sabo cebf8c167a Initial umbrella repo: thesis + FRET pipeline + plant model with first controllers

Folds three previously-separate pieces into one preliminary-example repo
for the HAHACS thesis:

- thesis/ (submodule) → gitea Thesis.git — the PhD proposal
- fret-pipeline/ — FRET requirements to AIGER controller (was
  ~/Documents/fret_processing/; prior single-commit history abandoned
  per user decision)
- plant-model/ — 10-state PKE + lumped T/H PWR model (was
  ~/Documents/PKE_Playground/; never version-controlled before)
- presentations/2026DICE/ (submodule) → gitea 2026DICE.git
- reachability/, hardware/ — empty placeholders for Thrust 3 and HIL
- docs/architecture.md — how the discrete and continuous layers compose
- claude_memory/ — session notes and scratch knowledge pattern

Plant model refactored to thesis naming (x, plant, u, ref); pke_th_rhs
now takes u as an explicit arg instead of reading rho_ext from the
params struct. First two controllers built to the contract
u = ctrl_<mode>(t, x, plant, ref): ctrl_null (baseline) and
ctrl_operation (stabilizing, proportional on T_avg). Validated under a
100% -> 80% Q_sg step: ctrl_operation reduces steady-state T_avg drift
~47% vs. the unforced plant.

Root CLAUDE.md emphasizes that CLAUDE.md files are living documents and
that any knowledge not captured before a session ends is lost forever;
claude_memory/ holds the session-level notes that haven't stabilized
enough to graduate into a CLAUDE.md.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

2026-04-16 16:24:11 -04:00

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visualize.sh -- AIGER Visualization Wrapper

Purpose

Convenience wrapper that renders an AIGER circuit as SVG/PNG using either aigtodot + Graphviz or Yosys. Handles tool detection and output directory creation.

Usage

bash scripts/visualize.sh <circuit.aag> [output_dir] [dot|yosys]

circuit.aag: the AIGER file to visualize
output_dir: where to write images (default: diagrams/)
Method: dot (default) or yosys

Methods

`dot` (default)

Requires aigtodot (from the AIGER tools) and graphviz. Produces a gate-level schematic.

Note: if aigtodot is not installed, use aag2dot.py instead:

python3 scripts/aag2dot.py circuits/SPEC.aag | dot -Tpng -o diagrams/SPEC.png

`yosys`

Requires Yosys and graphviz. Produces a higher-level schematic with recognized logic patterns (muxes, registers, etc.) drawn as compound symbols rather than individual gates.

Future Improvements

Auto-detect available tools: Fall back gracefully between aigtodot, aag2dot.py, and yosys depending on what's installed.
State machine mode: Add an option to invoke trace_aiger.py and render the behavioral state machine instead of the gate-level view.

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