Dane Sabo cebf8c167a Initial umbrella repo: thesis + FRET pipeline + plant model with first controllers

Folds three previously-separate pieces into one preliminary-example repo
for the HAHACS thesis:

- thesis/ (submodule) → gitea Thesis.git — the PhD proposal
- fret-pipeline/ — FRET requirements to AIGER controller (was
  ~/Documents/fret_processing/; prior single-commit history abandoned
  per user decision)
- plant-model/ — 10-state PKE + lumped T/H PWR model (was
  ~/Documents/PKE_Playground/; never version-controlled before)
- presentations/2026DICE/ (submodule) → gitea 2026DICE.git
- reachability/, hardware/ — empty placeholders for Thrust 3 and HIL
- docs/architecture.md — how the discrete and continuous layers compose
- claude_memory/ — session notes and scratch knowledge pattern

Plant model refactored to thesis naming (x, plant, u, ref); pke_th_rhs
now takes u as an explicit arg instead of reading rho_ext from the
params struct. First two controllers built to the contract
u = ctrl_<mode>(t, x, plant, ref): ctrl_null (baseline) and
ctrl_operation (stabilizing, proportional on T_avg). Validated under a
100% -> 80% Q_sg step: ctrl_operation reduces steady-state T_avg drift
~47% vs. the unforced plant.

Root CLAUDE.md emphasizes that CLAUDE.md files are living documents and
that any knowledge not captured before a session ends is lost forever;
claude_memory/ holds the session-level notes that haven't stabilized
enough to graduate into a CLAUDE.md.

Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>

2026-04-16 16:24:11 -04:00

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aag2dot.py -- Gate-Level Circuit Diagram

Purpose

Converts an ASCII AIGER (.aag) file into a Graphviz DOT representation showing the raw gate-level circuit topology. Unlike trace_aiger.py which shows the behavioral state machine, this shows the actual hardware structure: AND gates, latches, and wiring.

Usage

python3 scripts/aag2dot.py circuits/SPEC.aag | dot -Tsvg -o diagrams/SPEC_gates.svg

How It Works

`parse_aag(text)`

Same AIGER parsing logic as trace_aiger.py (see that documentation for format details). Returns a dictionary of inputs, latches, outputs, and AND gates.

`lit_node(lit)`

Maps an AIGER literal to a Graphviz node ID and negation flag:

Literal 14 -> ("n7", False) -- variable 7, positive
Literal 15 -> ("n7", True) -- variable 7, negated

`to_dot(aag)`

Generates the DOT string with:

Input nodes (light blue boxes): environment signals
Latch nodes (yellow rounded boxes): state registers
AND gate nodes (white circles): combinational logic
Output nodes (green boxes): controller outputs
Solid edges: positive connections
Dashed red edges with ~ label: negated connections
Feedback edges (constraint=false): latch next-state wiring, drawn backward to show the feedback loop

When to Use

The gate-level view is useful for:

Verifying the circuit structure matches expectations
Understanding how the synthesizer encoded the state transitions
Debugging unexpected behavior by tracing signals through gates
Presentations where you want to show "this is real hardware"

For understanding the controller's behavior (which mode transitions to which, under what conditions), use trace_aiger.py instead.

Future Improvements

Signal propagation highlighting: Color-code paths from a specific input to the outputs it affects.
Latch grouping: Visually group latches and their feedback logic into subclusters.
Gate count summary: Print statistics (number of each gate type, circuit depth, fan-in/fan-out).

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