78 lines
4.9 KiB
Markdown
78 lines
4.9 KiB
Markdown
The quick brown fox jumps over the lazy dog. The dog stays blissfully asleep. :)
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The goal of this project is to surpass sampling rate limitations of a successive
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approximation analog to digital converter by utilizing a modified
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observer to perform control on incomplete successive approximation data, while
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refining control based on latent sensor resolution.
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When a sensor makes an observation about a physical phenomena, the output of that
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sensor is a continuously changing value. Most modern control implementations,
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however, operate on computers that use a discrete space of values that can be
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expressed in memory. This creates an issue, where the continuous value of
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interest output by a sensor must be converted into a discrete equivalent that
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the controller can use. This step is processed by a special sensor interface
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circuit component called an analog to digital converter (ADC)
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\cite{modern_sensor_handbook}. ADCs jobs are to interpret the continuous signal
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of the sensor, and deliver the digital equivalent that can then be used for
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control.
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One type of ADC is especially common in microcontrollers today. The successive
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approximation (SAR) ADC converts analog signals to a digital equivalent by
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comparing the input voltage to a series of reference voltages controlled by
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a logical circuit. This conversion compares the input first to the most
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significant bit of the digital representation, and evaluates whether the
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input voltage is above or below the reference value. If the input voltage is
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higher than this value, the corresponding digital value must have a `1` in
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that location, while if the input voltage is less than the reference, it
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must have a `0` for that bit. The SAR ADC repeats this process for the number
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of bits required to complete a sample (usually about 12 bits). This series of
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comparisons happens one bit at a time, and must happen in the order of most
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significant bit to least significant bit.
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SAR ARC components must balance three competing design requirements: power
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usage, sampling speed, and noise rejection \cite{paper_about_adc}. The internal
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components of a SAR ADC are usually some configuration of capacitors that sample
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voltage from a certain instant, hold that sample throughout comparison, and
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perform the comparisons themselves. All of these processes take a significant
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amount of time complete, and due to the requirements of SAR ADCs to reject
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noise and limit power consumption, are difficult to speed up without incurring
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significant cost. These SAR ADC usually operate on their own internal clock
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that is much slower than the CPU clock on the broader controller. For example,
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the built-in ADC converters on the Atmel ATMega328P microcontroller commonly found
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in the Arduino Uno boards, has a maximum 10-bit analog to digital conversion
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rate of 15,000 samples per second. In comparison, the CPU on the ATmega328P can
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operate as quickly as 20 MHz when using an external clock \cite{ATmega_user_manual}.
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This means for a ATMega328P microcontroller utilizing ADC conversion, the CPU
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may spend a significant amount of time between control computations just waiting
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for an updated sensor value.
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There is potential that this waiting can be circumnavigated. If the memory
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registers of the SAR ADC can be accessed while it is actively building a
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sample, the first significant bits can be used in combination with a state
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estimation to perform control while the rest of the sample is still being
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generated. For this project, I will implement such a system.
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For this project, a simulated SAR ADC will be created. This simulated SAR ADC
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will be created to mimic the register behavior of the SAR ADC found on the
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ATMega328P, where the data registers are updated one by one on each clock cycle,
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and a flag register is utilized to indicate a conversion has finished. This
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simulated SAR ADC will be paired with a simulated controller fast enough to
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make state estimates and issue control commands between batches of ADC
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bits (3-4 bits per batch). This controller will estimate the state of the system
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at this partial-sample, and combined with the current ADC readout, perform control.
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For a plant, I plan to use the case of a read head on a hard disk drive. Hard
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disk drives require extreme precision to operate properly, and as such would
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benefit from an extremely high speed control system. In my problem, I will model
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this system as controlling the radial position of the read head, while modeling
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the inertia of the read head apparatus and motor dynamics. In addition to these
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effects, I will introduce a high frequency disturbance that represents turbulent
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fluid interacting with the drive head, pushing it off of its ideal position.
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The block diagram of this system is expressed in figure~\ref{fig}.
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If this project is successful, the higher inter-sample controller will have a
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lower average error between the real head position and desired head position
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when compared to the controller using only full ADC sampling.
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