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The quick brown fox jumps over the lazy dog. The dog stays blissfully asleep. :)
The goal of this project is to surpass sampling rate limitations of a successive approximation analog to digital converter by utilizing a modified observer to perform control on incomplete successive approximation data, while refining control based on latent sensor resolution.
When a sensor makes an observation about a physical phenomena, the output of that sensor is a continuously changing value. Most modern control implementations, however, operate on computers that use a discrete space of values that can be expressed in memory. This creates an issue, where the continuous value of interest output by a sensor must be converted into a discrete equivalent that the controller can use. This step is processed by a special sensor interface circuit component called an analog to digital converter (ADC) \cite{modern_sensor_handbook}. ADCs jobs are to interpret the continuous signal of the sensor, and deliver the digital equivalent that can then be used for control.
One type of ADC is especially common in microcontrollers today. The successive
approximation (SAR) ADC converts analog signals to a digital equivalent by
first storing the signal at an instant (a Zero-Order-Hold like operation), and
then compares the input voltage to a series of reference voltages controlled by
a logical circuit. This conversion compares the input first to the most
significant bit of the digital representation, and evaluates whether the
input voltage is above or below the reference value. If the input voltage is
higher than this value, the corresponding digital value must have a 1 in
that location, while if the input voltage is less than the reference, it
must have a 0 for that bit. The SAR ADC repeats this process for the number
of bits required to complete a sample (usually about 12 bits). This series of
comparisons happens one bit at a time, and must happen in the order of most
significant bit to least significant bit.
SAR ARC components must balance three competing design requirements: power usage, sampling speed, and noise rejection \cite{paper_about_adc}. The internal components of a SAR ADC are usually some configuration of capacitors that sample voltage from a certain instant, hold that sample throughout comparison, and perform the comparisons themselves. All of these processes take a significant amount of time complete, and due to the requirements of SAR ADCs to reject noise and limit power consumption, are difficult to speed up without incurring significant cost. These SAR ADC usually operate on their own internal clock that is much slower than the CPU clock on the broader controller. For example, the built-in ADC converters on the Atmel ATMega328P microcontroller commonly found in the Arduino Uno boards, has a maximum 10-bit analog to digital conversion rate of 15,000 samples per second. In comparison, the CPU on the ATmega328P can operate as quickly as 20 MHz when using an external clock \cite{ATmega_user_manual}. This means for a ATMega328P microcontroller utilizing ADC conversion, the CPU may spend a significant amount of time between control computations just waiting for an updated sensor value.
There is potential that this waiting can be circumnavigated. If the memory registers of the SAR ADC can be accessed while it is actively building a sample, the first significant bits can be used in combination with a state estimation to perform control while the rest of the sample is still being generated. For this project, I will implement such a system.
For this project, a simulated SAR ADC will be created. This simulated SAR ADC will be created to mimic the register behavior of the SAR ADC found on the ATMega328P, where the data registers are updated one by one on each clock cycle, and a flag register is utilized to indicate a conversion has finished. This simulated SAR ADC will be paired with a simulated controller fast enough to make state estimates and issue control commands between batches of ADC bits (3-4 bits per batch). This controller will estimate the state of the system at this partial-sample, and combined with the current ADC readout, perform control.
For a plant, I plan to use the case of a read head on a hard disk drive. Hard disk drives require extreme precision to operate properly, and as such would benefit from an extremely high speed control system. In my problem, I will model this system as controlling the radial position of the read head, while modeling the inertia of the read head apparatus and motor dynamics. In addition to these effects, I will introduce a high frequency disturbance that represents turbulent fluid interacting with the drive head, pushing it off of its ideal position. The block diagram of this system is expressed in figure~\ref{fig}.
If this project is successful, the higher inter-sample controller will have a lower average error between the real head position and desired head position when compared to the controller using only full ADC sampling.