M .task/backlog.data M .task/completed.data M .task/pending.data M .task/undo.data A PLAN_OF_STUDY_111225.pdf R Writing/202510270-Emerson-Pres/SaboOneSlide.pdf -> Presentations/202510270-Emerson-Pres/SaboOneSlide.pdf R Writing/202510270-Emerson-Pres/beamerthemedane.sty -> Presentations/202510270-Emerson-Pres/beamerthemedane.sty R Writing/202510270-Emerson-Pres/beamerthemedane_native.sty -> Presentations/202510270-Emerson-Pres/beamerthemedane_native.sty
61 lines
2.1 KiB
TeX
61 lines
2.1 KiB
TeX
% Expected Outcomes
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\begin{frame}{Success measured by progression to TRL 5---practical feasibility beyond theory}
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\begin{center}
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\begin{tikzpicture}[scale=0.9, transform shape]
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\draw[->, >=stealth, very thick] (0,0) -- (11,0) node[right] {TRL};
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% TRL markers
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\foreach \x/\label in {1/1, 3/2-3, 5.5/4, 8/5, 10/6} {
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\draw[thick] (\x,0.1) -- (\x,-0.1);
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\node[below] at (\x,-0.2) {\small\label};
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}
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% Starting point
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\node[circle, fill=red, minimum size=0.3cm, label=above:{\small Current}] at (3,0) {};
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\node[below=1cm of {(3,0)}, align=center, font=\tiny] {HARDENS\\TRL 3-4};
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% Target
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\node[circle, fill=green, minimum size=0.3cm, label=above:{\small\textbf{Target}}] at (8,0) {};
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\node[below=1cm of {(8,0)}, align=center, font=\tiny, text width=2.5cm] {Hardware-in-loop\\validated};
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% Arrow
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\draw[->, >=stealth, very thick, blue] (3.5,0.5) -- (7.5,0.5) node[midway, above] {\textbf{This Work}};
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\end{tikzpicture}
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\end{center}
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\vspace{0.5cm}
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\textbf{Three Deliverables:}
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\begin{enumerate}
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\item Procedure translation methodology
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\item Continuous verification framework
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\item SmAHTR demonstration on Emerson Ovation
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\end{enumerate}
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%SPEAKER NOTES: See comments below
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%
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\textbf{Technology Readiness Level Progression:}
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Current: TRL 2-3 (basic concepts, HARDENS precedent)
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Target: TRL 5 (validated prototype in relevant environment)
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\textbf{Three Concrete Deliverables:}
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1. Procedure Translation Methodology
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- Engineers generate verified controllers from regulatory procedures
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- No formal methods expertise required
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2. Continuous Verification Framework
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- Standard control design + iterative verification
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- Mathematical proof of safe mode transitions
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3. SmAHTR Hardware-in-the-Loop Demonstration
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- Autonomous startup on industrial control hardware
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- Real-time performance validation
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- Clear path to deployment
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\textbf{Key Message:} TRL 5 proves both theoretical validity and practical implementability
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% (End of speaker notes)
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\end{frame}
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