76 lines
4.6 KiB
TeX
76 lines
4.6 KiB
TeX
\section{Metrics for Success}
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This research will be measured by advancement through Technology Readiness
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Levels (TRL), progressing from fundamental concepts to validated prototype
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demonstration. TRLs measure the gap between academic proof-of-concept and
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practical deployment, which is precisely what this work aims to bridge. Academic
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metrics alone cannot capture practical feasibility, and empirical metrics alone
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cannot demonstrate theoretical rigor. TRLs measure both simultaneously. This
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work begins at TRL 2--3 and aims to reach TRL 5, where system components operate
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successfully in a relevant laboratory environment. This section explains why TRL
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advancement provides the most appropriate success metric and defines the
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specific criteria required to achieve TRL 5. Reaching TRL 5 provides a clear
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answer to industry questions about feasibility and maturity that academic
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publications alone cannot.
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Moving from current state to target requires achieving three intermediate
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levels, each representing a distinct validation milestone:
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\paragraph{TRL 3 \textit{Critical Function and Proof of Concept}}
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For this research, TRL 3 means demonstrating that each component of the
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methodology works in isolation. Startup procedures must be translated into
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temporal logic specifications that pass realizability analysis. A discrete
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automaton must be synthesized with interpretable structure. At least one
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continuous controller must be designed with reachability analysis proving
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transition requirements are satisfied. Independent review must confirm that
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specifications match intended procedural behavior. This proves the
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fundamental approach on a simplified startup sequence.
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\paragraph{TRL 4 \textit{Laboratory Testing of Integrated Components}}
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For this research, TRL 4 means demonstrating a complete integrated hybrid
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controller in simulation. All startup procedures must be formalized with a
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synthesized automaton covering all operational modes. Continuous controllers
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must exist for all discrete modes. Verification must be complete for all mode
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transitions using reachability analysis, barrier certificates, and
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assume-guarantee contracts. The integrated controller must execute complete
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startup sequences in software simulation with zero safety violations across
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multiple consecutive runs. This proves that formal correctness guarantees can
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be maintained throughout system integration.
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\paragraph{TRL 5 \textit{Laboratory Testing in Relevant Environment}}
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For this research, TRL 5 means demonstrating the verified controller on
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industrial control hardware through hardware-in-the-loop testing. The discrete
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automaton must be implemented on the Emerson Ovation control system and verified
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to match synthesized specifications exactly. Continuous controllers must execute
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at required rates. The ARCADE interface must establish stable real-time
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communication between the Emerson Ovation hardware and SmAHTR simulation.
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Complete autonomous startup sequences must execute via hardware-in-the-loop
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across the full operational envelope. The controller must handle off-nominal
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scenarios to validate that expulsory modes function correctly. For example,
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simulated sensor failures must trigger appropriate fault detection and mode
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transitions, and loss-of-cooling scenarios must activate SCRAM procedures as
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specified. Graded responses to minor disturbances are outside this work's scope,
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as they require runtime optimization under uncertainty that extends beyond the
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correct-by-construction verification framework presented here. Formal
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verification results must remain valid, with discrete behavior matching
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specifications and continuous trajectories remaining within verified bounds.
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This proves that the methodology produces verified controllers implementable on
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industrial hardware.
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Progress will be assessed quarterly through collection of specific data
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comparing actual results against TRL advancement criteria. Specification
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development status indicates progress toward TRL 3. Synthesis results and
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verification coverage indicate progress toward TRL 4. Simulation performance
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metrics and hardware integration milestones indicate progress toward TRL 5.
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The research plan will be revised only when new data invalidates fundamental
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assumptions. This research succeeds if it achieves TRL 5 by demonstrating a
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complete autonomous hybrid controller with formal correctness guarantees
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operating on industrial control hardware through hardware-in-the-loop
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testing in a relevant laboratory environment. This establishes both
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theoretical validity and practical feasibility, proving that the methodology
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produces verified controllers and that implementation is achievable with
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current technology.
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