Auto sync: 2025-09-09 18:42:41 (6 files changed)
M .sessions/nvim_config.vim A .task/backlog.data A .task/completed.data A .task/pending.data A .task/undo.data A Writing/ERLM/state-of-the-art/outline.md
This commit is contained in:
parent
87b28b6113
commit
ea9b1f2b16
@ -13,14 +13,33 @@ if &shortmess =~ 'A'
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else
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else
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set shortmess=aoO
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set shortmess=aoO
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endif
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endif
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badd +12 ~/.config/nvim/lua/custom/plugins.lua
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badd +44 custom/configs/lspconfig.lua
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badd +44 custom/configs/lspconfig.lua
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badd +89 custom/journal.lua
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badd +1 custom/taskwarrior.lua
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badd +11 custom/init.lua
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badd +203 ~/.config/nvim/lua/custom/plugins.lua
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argglobal
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argglobal
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%argdel
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%argdel
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edit custom/journal.lua
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edit ~/.config/nvim/lua/custom/plugins.lua
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let s:save_splitbelow = &splitbelow
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let s:save_splitright = &splitright
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set splitbelow splitright
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wincmd _ | wincmd |
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vsplit
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1wincmd h
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wincmd w
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let &splitbelow = s:save_splitbelow
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let &splitright = s:save_splitright
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wincmd t
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let s:save_winminheight = &winminheight
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let s:save_winminwidth = &winminwidth
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set winminheight=0
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set winheight=1
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set winminwidth=0
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set winwidth=1
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exe 'vert 1resize ' . ((&columns * 95 + 95) / 190)
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exe 'vert 2resize ' . ((&columns * 94 + 95) / 190)
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argglobal
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argglobal
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balt ~/.config/nvim/lua/custom/plugins.lua
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balt custom/configs/lspconfig.lua
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setlocal foldmethod=manual
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setlocal foldmethod=manual
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setlocal foldexpr=v:lua.vim.treesitter.foldexpr()
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setlocal foldexpr=v:lua.vim.treesitter.foldexpr()
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setlocal foldmarker={{{,}}}
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setlocal foldmarker={{{,}}}
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@ -31,12 +50,38 @@ setlocal foldnestmax=20
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setlocal foldenable
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setlocal foldenable
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silent! normal! zE
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silent! normal! zE
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let &fdl = &fdl
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let &fdl = &fdl
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let s:l = 89 - ((11 * winheight(0) + 23) / 47)
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let s:l = 203 - ((53 * winheight(0) + 30) / 60)
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if s:l < 1 | let s:l = 1 | endif
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if s:l < 1 | let s:l = 1 | endif
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keepjumps exe s:l
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keepjumps exe s:l
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normal! zt
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normal! zt
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keepjumps 89
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keepjumps 203
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normal! 016|
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normal! 016|
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wincmd w
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argglobal
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if bufexists(fnamemodify("custom/taskwarrior.lua", ":p")) | buffer custom/taskwarrior.lua | else | edit custom/taskwarrior.lua | endif
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if &buftype ==# 'terminal'
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silent file custom/taskwarrior.lua
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endif
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balt custom/configs/lspconfig.lua
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setlocal foldmethod=manual
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setlocal foldexpr=v:lua.vim.treesitter.foldexpr()
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setlocal foldmarker={{{,}}}
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setlocal foldignore=#
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setlocal foldlevel=0
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setlocal foldminlines=1
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setlocal foldnestmax=20
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setlocal foldenable
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silent! normal! zE
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let &fdl = &fdl
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let s:l = 280 - ((43 * winheight(0) + 30) / 60)
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if s:l < 1 | let s:l = 1 | endif
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keepjumps exe s:l
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normal! zt
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keepjumps 280
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normal! 09|
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wincmd w
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exe 'vert 1resize ' . ((&columns * 95 + 95) / 190)
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exe 'vert 2resize ' . ((&columns * 94 + 95) / 190)
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tabnext 1
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tabnext 1
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if exists('s:wipebuf') && len(win_findbuf(s:wipebuf)) == 0 && getbufvar(s:wipebuf, '&buftype') isnot# 'terminal'
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if exists('s:wipebuf') && len(win_findbuf(s:wipebuf)) == 0 && getbufvar(s:wipebuf, '&buftype') isnot# 'terminal'
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silent exe 'bwipe ' . s:wipebuf
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silent exe 'bwipe ' . s:wipebuf
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@ -44,6 +89,8 @@ endif
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unlet! s:wipebuf
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unlet! s:wipebuf
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set winheight=1 winwidth=20
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set winheight=1 winwidth=20
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let &shortmess = s:shortmess_save
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let &shortmess = s:shortmess_save
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let &winminheight = s:save_winminheight
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let &winminwidth = s:save_winminwidth
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let s:sx = expand("<sfile>:p:r")."x.vim"
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let s:sx = expand("<sfile>:p:r")."x.vim"
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if filereadable(s:sx)
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if filereadable(s:sx)
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exe "source " . fnameescape(s:sx)
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exe "source " . fnameescape(s:sx)
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24
.task/backlog.data
Normal file
24
.task/backlog.data
Normal file
@ -0,0 +1,24 @@
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{"description":"learn taskmaster","entry":"20250909T172539Z","modified":"20250909T172539Z","status":"pending","uuid":"b4945a12-909c-47cc-8779-e3f8f917181c"}
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{"description":"try taskmaster","entry":"20250909T172547Z","modified":"20250909T172547Z","status":"pending","uuid":"a56a03cd-36ec-4786-907b-77d8d162426d"}
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{"description":"learn taskmaster","end":"20250909T172616Z","entry":"20250909T172539Z","modified":"20250909T172616Z","status":"completed","uuid":"b4945a12-909c-47cc-8779-e3f8f917181c"}
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{"description":"try taskmaster","end":"20250909T172619Z","entry":"20250909T172547Z","modified":"20250909T172619Z","status":"completed","uuid":"a56a03cd-36ec-4786-907b-77d8d162426d"}
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{"description":"Write outline for SOTA project:ERLM due:today","entry":"20250909T180102Z","modified":"20250909T180102Z","status":"pending","uuid":"3dfe52e3-749b-4d6b-9a01-2b078ddd968a"}
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{"description":"Write outline for SOTA project:ERLM due:today","due":"20250909T040000Z","entry":"20250909T180102Z","modified":"20250909T180217Z","project":"ERLM,","status":"pending","uuid":"3dfe52e3-749b-4d6b-9a01-2b078ddd968a"}
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{"description":"Literature review of rchapter 2 project:dissertation priority:H +reading due:friday","entry":"20250909T180633Z","modified":"20250909T180633Z","status":"pending","uuid":"864d1a2e-7343-403a-80e6-d95bff22d90b"}
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{"description":"Literature review","due":"20250912T040000Z","entry":"20250909T180832Z","modified":"20250909T180832Z","priority":"H","project":"dissertation","status":"pending","uuid":"670b304a-2f18-47b9-beb3-b0aa7eb38e57","tags":["reading"]}
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{"description":"fix pid controller","entry":"20250909T181356Z","modified":"20250909T181356Z","project":"research","status":"pending","uuid":"91f80e7a-7a7b-4f45-9593-872ba04039d7","tags":["coding","urgent"]}
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{"description":"hellow!","entry":"20250909T181900Z","modified":"20250909T181900Z","status":"pending","uuid":"1ee492ad-9e81-4b01-b062-2f4d166a7865"}
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{"description":"hellow testing","entry":"20250909T182122Z","modified":"20250909T182122Z","status":"pending","uuid":"44d5c3a3-d97b-4ef2-a0ab-de5d562830d3"}
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{"description":"testing","entry":"20250909T182418Z","modified":"20250909T182418Z","status":"pending","uuid":"9e4fb42e-8427-4f8a-9405-291de01f2425"}
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{"description":"testing testing","entry":"20250909T183241Z","modified":"20250909T183241Z","project":"urmom","status":"pending","uuid":"5c094262-eb5e-4763-927b-1919c03d9790"}
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{"description":"Write outline for state of the art","due":"20250910T040000Z","entry":"20250909T183935Z","modified":"20250909T183935Z","project":"ERLM","status":"pending","uuid":"8e7a8e19-9197-4008-b7d9-521ffcf7ba91"}
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{"description":"Write zettels about Andre Platzer and differential dynamic logic","entry":"20250909T184010Z","modified":"20250909T184010Z","project":"zk","status":"pending","uuid":"74f33a56-3525-47d2-aa8c-fcb9488c7726"}
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{"description":"Write zettels about webofscience database","entry":"20250909T184042Z","modified":"20250909T184042Z","project":"zk","status":"pending","uuid":"9cb17c85-f1e6-4280-86da-a5af8f229b15"}
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{"description":"Look over obsidian tasks and see if anything is worth moving over","entry":"20250909T184102Z","modified":"20250909T184102Z","status":"pending","uuid":"c1a5390d-5b84-4f9c-8acb-ffb970682660","tags":["taskwarrior"]}
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{"description":"Follow up with Daniel about controls bootcamp","due":"20250911T040000Z","entry":"20250909T201850Z","modified":"20250909T201850Z","project":"FSAE","status":"pending","uuid":"3eaadead-4e5e-4823-9077-16d6e1800862"}
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{"description":"Follow up with Bajaj about writing TurboSAR paper","due":"20250911T040000Z","entry":"20250909T202126Z","modified":"20250909T202126Z","status":"pending","uuid":"fa2699f9-0082-433e-ae0d-cc2553db9865"}
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{"description":"Follow up with Bajaj about writing TurboSAR paper","due":"20250911T040000Z","entry":"20250909T202126Z","modified":"20250909T202243Z","priority":"L","status":"pending","uuid":"fa2699f9-0082-433e-ae0d-cc2553db9865"}
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{"description":"Look around for summer internships with national labs","entry":"20250909T202851Z","modified":"20250909T202851Z","status":"pending","uuid":"d3f3dc53-4feb-4b7e-8de5-86ebf3c535d5"}
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{"description":"Write first draft of state of the art","due":"20250912T040000Z","entry":"20250909T203258Z","modified":"20250909T203258Z","project":"ERLM","status":"pending","uuid":"4bec1530-18bc-43cb-9f0b-61e35dbf1730","tags":["writing"],"depends":["8e7a8e19-9197-4008-b7d9-521ffcf7ba91"]}
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{"description":"Write outline for state of the art","due":"20250910T040000Z","entry":"20250909T183935Z","modified":"20250909T203502Z","project":"ERLM","start":"20250909T203502Z","status":"pending","uuid":"8e7a8e19-9197-4008-b7d9-521ffcf7ba91"}
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{"description":"Write outline for state of the art","due":"20250910T040000Z","entry":"20250909T183935Z","modified":"20250909T210227Z","project":"ERLM","status":"pending","uuid":"8e7a8e19-9197-4008-b7d9-521ffcf7ba91"}
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2
.task/completed.data
Normal file
2
.task/completed.data
Normal file
@ -0,0 +1,2 @@
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[description:"learn taskmaster" end:"1757438776" entry:"1757438739" modified:"1757438776" status:"completed" uuid:"b4945a12-909c-47cc-8779-e3f8f917181c"]
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[description:"try taskmaster" end:"1757438779" entry:"1757438747" modified:"1757438779" status:"completed" uuid:"a56a03cd-36ec-4786-907b-77d8d162426d"]
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8
.task/pending.data
Normal file
8
.task/pending.data
Normal file
@ -0,0 +1,8 @@
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[description:"Write outline for state of the art" due:"1757476800" entry:"1757443175" modified:"1757451747" project:"ERLM" status:"pending" uuid:"8e7a8e19-9197-4008-b7d9-521ffcf7ba91"]
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[description:"Write zettels about Andre Platzer and differential dynamic logic" entry:"1757443210" modified:"1757443210" project:"zk" status:"pending" uuid:"74f33a56-3525-47d2-aa8c-fcb9488c7726"]
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[description:"Write zettels about webofscience database" entry:"1757443242" modified:"1757443242" project:"zk" status:"pending" uuid:"9cb17c85-f1e6-4280-86da-a5af8f229b15"]
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[description:"Look over obsidian tasks and see if anything is worth moving over" entry:"1757443262" modified:"1757443262" status:"pending" tags:"taskwarrior" tags_taskwarrior:"x" uuid:"c1a5390d-5b84-4f9c-8acb-ffb970682660"]
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[description:"Follow up with Daniel about controls bootcamp" due:"1757563200" entry:"1757449130" modified:"1757449130" project:"FSAE" status:"pending" uuid:"3eaadead-4e5e-4823-9077-16d6e1800862"]
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[description:"Follow up with Bajaj about writing TurboSAR paper" due:"1757563200" entry:"1757449286" modified:"1757449363" priority:"L" status:"pending" uuid:"fa2699f9-0082-433e-ae0d-cc2553db9865"]
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[description:"Look around for summer internships with national labs" entry:"1757449731" modified:"1757449731" status:"pending" uuid:"d3f3dc53-4feb-4b7e-8de5-86ebf3c535d5"]
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[dep_8e7a8e19-9197-4008-b7d9-521ffcf7ba91:"x" depends:"8e7a8e19-9197-4008-b7d9-521ffcf7ba91" description:"Write first draft of state of the art" due:"1757649600" entry:"1757449978" modified:"1757449978" project:"ERLM" status:"pending" tags:"writing" tags_writing:"x" uuid:"4bec1530-18bc-43cb-9f0b-61e35dbf1730"]
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78
.task/undo.data
Normal file
78
.task/undo.data
Normal file
@ -0,0 +1,78 @@
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time 1757438739
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new [description:"learn taskmaster" entry:"1757438739" modified:"1757438739" status:"pending" uuid:"b4945a12-909c-47cc-8779-e3f8f917181c"]
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---
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time 1757438747
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new [description:"try taskmaster" entry:"1757438747" modified:"1757438747" status:"pending" uuid:"a56a03cd-36ec-4786-907b-77d8d162426d"]
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---
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time 1757438776
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old [description:"learn taskmaster" entry:"1757438739" modified:"1757438739" status:"pending" uuid:"b4945a12-909c-47cc-8779-e3f8f917181c"]
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new [description:"learn taskmaster" end:"1757438776" entry:"1757438739" modified:"1757438776" status:"completed" uuid:"b4945a12-909c-47cc-8779-e3f8f917181c"]
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---
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time 1757438779
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old [description:"try taskmaster" entry:"1757438747" modified:"1757438747" status:"pending" uuid:"a56a03cd-36ec-4786-907b-77d8d162426d"]
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new [description:"try taskmaster" end:"1757438779" entry:"1757438747" modified:"1757438779" status:"completed" uuid:"a56a03cd-36ec-4786-907b-77d8d162426d"]
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---
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time 1757440862
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new [description:"Write outline for SOTA project:ERLM due:today" entry:"1757440862" modified:"1757440862" status:"pending" uuid:"3dfe52e3-749b-4d6b-9a01-2b078ddd968a"]
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---
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time 1757440937
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old [description:"Write outline for SOTA project:ERLM due:today" entry:"1757440862" modified:"1757440862" status:"pending" uuid:"3dfe52e3-749b-4d6b-9a01-2b078ddd968a"]
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new [description:"Write outline for SOTA project:ERLM due:today" due:"1757390400" entry:"1757440862" modified:"1757440937" project:"ERLM," status:"pending" uuid:"3dfe52e3-749b-4d6b-9a01-2b078ddd968a"]
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---
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time 1757441193
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new [description:"Literature review of rchapter 2 project:dissertation priority:H +reading due:friday" entry:"1757441193" modified:"1757441193" status:"pending" uuid:"864d1a2e-7343-403a-80e6-d95bff22d90b"]
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---
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time 1757441312
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new [description:"Literature review" due:"1757649600" entry:"1757441312" modified:"1757441312" priority:"H" project:"dissertation" status:"pending" tags:"reading" tags_reading:"x" uuid:"670b304a-2f18-47b9-beb3-b0aa7eb38e57"]
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---
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time 1757441636
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new [description:"fix pid controller" entry:"1757441636" modified:"1757441636" project:"research" status:"pending" tags:"coding,urgent" tags_coding:"x" tags_urgent:"x" uuid:"91f80e7a-7a7b-4f45-9593-872ba04039d7"]
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---
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time 1757441940
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new [description:"hellow!" entry:"1757441940" modified:"1757441940" status:"pending" uuid:"1ee492ad-9e81-4b01-b062-2f4d166a7865"]
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---
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time 1757442082
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new [description:"hellow testing" entry:"1757442082" modified:"1757442082" status:"pending" uuid:"44d5c3a3-d97b-4ef2-a0ab-de5d562830d3"]
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---
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time 1757442258
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new [description:"testing" entry:"1757442258" modified:"1757442258" status:"pending" uuid:"9e4fb42e-8427-4f8a-9405-291de01f2425"]
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---
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time 1757442761
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new [description:"testing testing" entry:"1757442761" modified:"1757442761" project:"urmom" status:"pending" uuid:"5c094262-eb5e-4763-927b-1919c03d9790"]
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---
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time 1757443175
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new [description:"Write outline for state of the art" due:"1757476800" entry:"1757443175" modified:"1757443175" project:"ERLM" status:"pending" uuid:"8e7a8e19-9197-4008-b7d9-521ffcf7ba91"]
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---
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time 1757443210
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new [description:"Write zettels about Andre Platzer and differential dynamic logic" entry:"1757443210" modified:"1757443210" project:"zk" status:"pending" uuid:"74f33a56-3525-47d2-aa8c-fcb9488c7726"]
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---
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time 1757443242
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new [description:"Write zettels about webofscience database" entry:"1757443242" modified:"1757443242" project:"zk" status:"pending" uuid:"9cb17c85-f1e6-4280-86da-a5af8f229b15"]
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---
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time 1757443262
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new [description:"Look over obsidian tasks and see if anything is worth moving over" entry:"1757443262" modified:"1757443262" status:"pending" tags:"taskwarrior" tags_taskwarrior:"x" uuid:"c1a5390d-5b84-4f9c-8acb-ffb970682660"]
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---
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time 1757449130
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new [description:"Follow up with Daniel about controls bootcamp" due:"1757563200" entry:"1757449130" modified:"1757449130" project:"FSAE" status:"pending" uuid:"3eaadead-4e5e-4823-9077-16d6e1800862"]
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---
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time 1757449286
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new [description:"Follow up with Bajaj about writing TurboSAR paper" due:"1757563200" entry:"1757449286" modified:"1757449286" status:"pending" uuid:"fa2699f9-0082-433e-ae0d-cc2553db9865"]
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---
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time 1757449363
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old [description:"Follow up with Bajaj about writing TurboSAR paper" due:"1757563200" entry:"1757449286" modified:"1757449286" status:"pending" uuid:"fa2699f9-0082-433e-ae0d-cc2553db9865"]
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new [description:"Follow up with Bajaj about writing TurboSAR paper" due:"1757563200" entry:"1757449286" modified:"1757449363" priority:"L" status:"pending" uuid:"fa2699f9-0082-433e-ae0d-cc2553db9865"]
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---
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time 1757449731
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new [description:"Look around for summer internships with national labs" entry:"1757449731" modified:"1757449731" status:"pending" uuid:"d3f3dc53-4feb-4b7e-8de5-86ebf3c535d5"]
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new [dep_8e7a8e19-9197-4008-b7d9-521ffcf7ba91:"x" depends:"8e7a8e19-9197-4008-b7d9-521ffcf7ba91" description:"Write first draft of state of the art" due:"1757649600" entry:"1757449978" modified:"1757449978" project:"ERLM" status:"pending" tags:"writing" tags_writing:"x" uuid:"4bec1530-18bc-43cb-9f0b-61e35dbf1730"]
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new [description:"Write outline for state of the art" due:"1757476800" entry:"1757443175" modified:"1757450102" project:"ERLM" start:"1757450102" status:"pending" uuid:"8e7a8e19-9197-4008-b7d9-521ffcf7ba91"]
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old [description:"Write outline for state of the art" due:"1757476800" entry:"1757443175" modified:"1757450102" project:"ERLM" start:"1757450102" status:"pending" uuid:"8e7a8e19-9197-4008-b7d9-521ffcf7ba91"]
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new [description:"Write outline for state of the art" due:"1757476800" entry:"1757443175" modified:"1757451747" project:"ERLM" status:"pending" uuid:"8e7a8e19-9197-4008-b7d9-521ffcf7ba91"]
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Writing/ERLM/state-of-the-art/outline.md
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# Outline of State of the Art
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## Writing is thinking, and this is like journaling
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This research is really about using techniques that we
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already have to make hybrid systems that from the jump are
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provably adherent to requirements and in general that we can
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say what they're gonna do fo sho. Does that make any sense?
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The critical technologies to do this are as follows, in no
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particular order: discrete system theory and reactive
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|
synthesis, temporal logics, reachability for hybrid systems.
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|
|
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|
Things that are adjacent to what I'm doing but aren't what
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I'm doing include stuff by Platzer and all the differential
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|
dynamic logic stuff. His stuff looks like another way of
|
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|
conquering this problem but adds a whole lot of complexity
|
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|
and makes synthesis ambiguous. Great at checking, but what
|
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|
does that mean for designing?
|
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|
|
||||||
|
I feel like I should get more sources on designing hybrid
|
||||||
|
systems. I think there are some books out there about this
|
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|
maybe.
|
||||||
|
|
||||||
|
----
|
||||||
|
**Outline**
|
||||||
|
----
|
||||||
|
|
||||||
|
## 1. Hybrid Control Systems Foundations
|
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|
- **Classical hybrid systems theory** (Branicky, Liberzon,
|
||||||
|
Morse - switching systems)
|
||||||
|
- **Hybrid automata and modeling** (Henzinger, Alur, Dill)
|
||||||
|
- **Stability analysis for switching systems** (Shorten,
|
||||||
|
Narendra, Lin & Antsaklis)
|
||||||
|
|
||||||
|
**Key points to include:**
|
||||||
|
- Definition of hybrid systems and why they're needed for
|
||||||
|
complex control
|
||||||
|
- Challenges in stability analysis when switching between
|
||||||
|
controllers
|
||||||
|
- Gap between individual mode stability and overall system
|
||||||
|
stability
|
||||||
|
- Motivate why traditional control theory alone is
|
||||||
|
insufficient
|
||||||
|
|
||||||
|
## 2. Discrete Controller Synthesis
|
||||||
|
- **Reactive synthesis from temporal logic** (Pnueli, Bloem,
|
||||||
|
Ehlers)
|
||||||
|
- **Tools like Strix, TuLiP, SLUGS** - emphasize their
|
||||||
|
discrete-only assumptions
|
||||||
|
- **LTL/GR(1) synthesis** and why these assume instantaneous
|
||||||
|
transitions
|
||||||
|
|
||||||
|
**Key points to include:**
|
||||||
|
- Power of temporal logic for specifying complex behaviors
|
||||||
|
- Success of reactive synthesis in discrete domains
|
||||||
|
- Correctness-by-construction guarantees from synthesis
|
||||||
|
tools
|
||||||
|
- Critical limitation: assumption of instantaneous state
|
||||||
|
changes
|
||||||
|
- Why this breaks down for physical systems with continuous
|
||||||
|
dynamics
|
||||||
|
|
||||||
|
## 3. Continuous System Verification
|
||||||
|
- **Reachability analysis** (Girard, Le Guernic, Althoff -
|
||||||
|
especially for nonlinear systems)
|
||||||
|
- **Linear system verification** (Boyd, Dullerud - classical
|
||||||
|
control meets verification)
|
||||||
|
- **Set-based methods** (Mitchell, Tomlin for
|
||||||
|
Hamilton-Jacobi reachability)
|
||||||
|
|
||||||
|
**Key points to include:**
|
||||||
|
- Mature tools for analyzing continuous dynamics
|
||||||
|
- Reachability as the fundamental verification problem
|
||||||
|
- Computational challenges for nonlinear systems
|
||||||
|
- Gap: these are analysis tools, not synthesis tools
|
||||||
|
- They tell you if a controller works, but don't help design
|
||||||
|
it
|
||||||
|
|
||||||
|
## 4. Existing Hybrid Verification Approaches
|
||||||
|
- **Platzer's differential dynamic logic** (as you noted -
|
||||||
|
good for verification, unclear for synthesis)
|
||||||
|
- **SpaceEx, Flow*, dReach** - model checking tools that
|
||||||
|
don't synthesize
|
||||||
|
- **Contract-based design** (Benveniste,
|
||||||
|
Sangiovanni-Vincentelli)
|
||||||
|
|
||||||
|
**Key points to include:**
|
||||||
|
- Current approaches focus on verification after design
|
||||||
|
- Platzer's dL: powerful for proving correctness, but
|
||||||
|
synthesis unclear
|
||||||
|
- Model checking tools require pre-designed controllers
|
||||||
|
- Contract-based approaches: compositional but still
|
||||||
|
verification-focused
|
||||||
|
- Missing: unified synthesis framework that handles both
|
||||||
|
discrete and continuous
|
||||||
|
|
||||||
|
## 5. The Gap You're Filling
|
||||||
|
- **Why discrete synthesis + continuous verification hasn't
|
||||||
|
been unified**
|
||||||
|
- **Challenges with non-instantaneous transitions**
|
||||||
|
- **The synthesis vs. verification divide**
|
||||||
|
|
||||||
|
**Key points to include:**
|
||||||
|
- Fundamental mismatch: discrete synthesis assumes instant
|
||||||
|
transitions
|
||||||
|
- Physical reality: transitions take time and follow
|
||||||
|
continuous trajectories
|
||||||
|
- Current workflow: synthesize discrete, design continuous,
|
||||||
|
then verify
|
||||||
|
- Your contribution: unified framework for
|
||||||
|
correct-by-construction hybrid synthesis
|
||||||
|
- Nuclear startup as ideal testbed: well-defined continuous
|
||||||
|
dynamics + explicit procedural requirements
|
||||||
|
|
||||||
|
## Key Sources to Hunt Down
|
||||||
|
|
||||||
|
**Foundational hybrid systems:**
|
||||||
|
- Branicky's "Multiple Lyapunov functions and other analysis
|
||||||
|
tools"
|
||||||
|
- Liberzon's "Switching in Systems and Control"
|
||||||
|
- Antsaklis & Koutsoukos survey papers
|
||||||
|
|
||||||
|
**Reactive synthesis:**
|
||||||
|
- Ehlers & Topcu on GR(1) synthesis
|
||||||
|
- Recent Strix papers (Meyer, Sickert, Luttenberger)
|
||||||
|
- Wongpiromsarn's work on TuLiP
|
||||||
|
|
||||||
|
**Hybrid verification:**
|
||||||
|
- Althoff's reachability analysis work
|
||||||
|
- Girard's papers on abstraction-based verification
|
||||||
|
- Any recent survey on hybrid system verification tools
|
||||||
|
|
||||||
|
**Nuclear/critical systems control:**
|
||||||
|
- Look for papers on autonomous nuclear plant operation
|
||||||
|
- Regulatory papers on control system requirements (might be
|
||||||
|
more engineering sources)
|
||||||
|
|
||||||
Loading…
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Reference in New Issue
Block a user