diff --git a/.sessions/Digital_Control_Theory.vim b/.sessions/Digital_Control_Theory.vim
index ff5c6297..03ac23fe 100644
--- a/.sessions/Digital_Control_Theory.vim
+++ b/.sessions/Digital_Control_Theory.vim
@@ -13,10 +13,11 @@ if &shortmess =~ 'A'
 else
   set shortmess=aoO
 endif
+badd +32 Project/Project_Proposal.md
 argglobal
 %argdel
+edit Project/Project_Proposal.md
 argglobal
-enew
 setlocal fdm=manual
 setlocal fde=0
 setlocal fmr={{{,}}}
@@ -25,6 +26,17 @@ setlocal fdl=0
 setlocal fml=1
 setlocal fdn=20
 setlocal fen
+silent! normal! zE
+32,47fold
+let &fdl = &fdl
+32
+normal! zo
+let s:l = 32 - ((17 * winheight(0) + 27) / 55)
+if s:l < 1 | let s:l = 1 | endif
+keepjumps exe s:l
+normal! zt
+keepjumps 32
+normal! 0
 tabnext 1
 if exists('s:wipebuf') && len(win_findbuf(s:wipebuf)) == 0 && getbufvar(s:wipebuf, '&buftype') isnot# 'terminal'
   silent exe 'bwipe ' . s:wipebuf
diff --git a/.sessions/nvim_config.vim b/.sessions/nvim_config.vim
index 083f46d1..ae0c6395 100644
--- a/.sessions/nvim_config.vim
+++ b/.sessions/nvim_config.vim
@@ -14,14 +14,15 @@ else
   set shortmess=aoO
 endif
 badd +17 ~/.config/nvim/lua/custom/plugins.lua
-badd +9 ~/.config/nvim/lua/custom/configs/lspconfig.lua
+badd +33 ~/.config/nvim/lua/custom/configs/lspconfig.lua
 badd +6 custom/configs/rust-tools.lua
-badd +4 custom/init.lua
+badd +5 custom/init.lua
+badd +91 ~/.config/nvim/lua/custom/chadrc.lua
 argglobal
 %argdel
 edit custom/init.lua
 argglobal
-balt ~/.config/nvim/lua/custom/configs/lspconfig.lua
+balt ~/.config/nvim/lua/custom/chadrc.lua
 setlocal fdm=manual
 setlocal fde=0
 setlocal fmr={{{,}}}
@@ -32,12 +33,12 @@ setlocal fdn=20
 setlocal fen
 silent! normal! zE
 let &fdl = &fdl
-let s:l = 4 - ((3 * winheight(0) + 32) / 64)
+let s:l = 11 - ((10 * winheight(0) + 27) / 55)
 if s:l < 1 | let s:l = 1 | endif
 keepjumps exe s:l
 normal! zt
-keepjumps 4
-normal! 028|
+keepjumps 11
+normal! 0
 tabnext 1
 if exists('s:wipebuf') && len(win_findbuf(s:wipebuf)) == 0 && getbufvar(s:wipebuf, '&buftype') isnot# 'terminal'
   silent exe 'bwipe ' . s:wipebuf
diff --git a/300s School/ME 2046 - Digital Control Theory/Project/Project_Proposal.md b/300s School/ME 2046 - Digital Control Theory/Project/Project_Proposal.md
index bce90b6b..21b6f916 100644
--- a/300s School/ME 2046 - Digital Control Theory/Project/Project_Proposal.md	
+++ b/300s School/ME 2046 - Digital Control Theory/Project/Project_Proposal.md	
@@ -12,7 +12,7 @@ expressed in memory. This creates an issue, where the continuous value of
 interest output by a sensor must be converted into a discrete equivalent that 
 the controller can use. This step is processed by a special sensor interface
 circuit component called an analog to digital converter (ADC) 
-\cite{modern_sensor_handbook}. ADCs job are to interpret the continuous signal
+\cite{modern_sensor_handbook}. ADCs jobs are to interpret the continuous signal
 of the sensor, and deliver the digital equivalent that can then be used for
 control.
 
@@ -24,14 +24,14 @@ significant bit of the digital representation, and evaluates whether the
 input voltage is above or below the reference value. If the input voltage is
 higher than this value, the corresponding digital value must have a `1` in 
 that location, while if the input voltage is less than the reference, it 
-must have a `0` for that bit. The SAR ADC repeates this process for the number 
+must have a `0` for that bit. The SAR ADC repeats this process for the number 
 of bits required to complete a sample (usually about 12 bits). This series of
 comparisons happens one bit at a time, and must happen in the order of most
 significant bit to least significant bit.
 
 SAR ARC components must balance three competing design requirements: power 
 usage, sampling speed, and noise rejection \cite{paper_about_adc}. The internal
-components of a SAR ADC are usually some configuration of capicitors that sample
+components of a SAR ADC are usually some configuration of capacitors that sample
 voltage from a certain instant, hold that sample throughout comparison, and 
 perform the comparisons themselves. All of these processes take a significant
 amount of time complete, and due to the requirements of SAR ADCs to reject 
@@ -46,4 +46,17 @@ This means for a ATMega328P microcontroller utilizing ADC conversion, the CPU
 may spend a significant amount of time between control computations just waiting
 for an updated sensor value.
 
-There is potential that this waiting can be circumnavigated. *explain how SAR updates registers continuously for some devices. perhaps we can use first couple bits with a state estimator to make a guess what the final value will be and do control. then as we get mroe info, and with our model of the system, we can correct for how wrong we were*
+There is potential that this waiting can be circumnavigated. If the memory 
+registers of the SAR ADC can be accessed while it is actively building a 
+sample, the first significant bits can be used in combination with a state 
+estimation to perform control while the rest of the sample is still being 
+generated. For this project, I will implement such a system.
+
+For this project, a simulated SAR ADC will be created. This simulated SAR ADC
+will be created to mimic the register behavior of the SAR ADC found on the 
+ATMega328P, where the data registers are updated one by one on each clock cycle,
+and a flag register is utilized to indicate a conversion has finished. This 
+simulated SAR ADC will be paired with a simulated controller operating 
+
+*explain how SAR updates registers continuously for some devices. perhaps we can use first couple bits with a state estimator to make a guess what the final value will be and do control. then as we get mroe info, and with our model of the system, we can correct for how wrong we were*
+
diff --git a/900s Calendars/Learning/2025-03-26 ME 2046 Project Proposal.md b/900s Calendars/Learning/2025-03-26 ME 2046 Project Proposal.md
new file mode 100644
index 00000000..fc50c627
--- /dev/null
+++ b/900s Calendars/Learning/2025-03-26 ME 2046 Project Proposal.md	
@@ -0,0 +1,8 @@
+---
+title: ME 2046 Project Proposal
+allDay: false
+startTime: 13:30
+endTime: 15:45
+date: 2025-03-26
+completed: null
+---