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Dane Sabo 2025-03-27 15:22:46 -04:00
parent 3525672553
commit b6a5b87081
4 changed files with 212 additions and 11 deletions
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198
.obsidian/workspaces.json vendored Normal file
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@ -0,0 +1,198 @@
{
"workspaces": {
"task_master": {
"main": {
"id": "9acdaefd89bfd05b",
"type": "split",
"children": [
{
"id": "7860a3855250521b",
"type": "tabs",
"children": [
{
"id": "f446cb1a27f0bd59",
"type": "leaf",
"state": {
"type": "markdown",
"state": {
"file": "0 Managerial Pages/1 Task Dashboard.md",
"mode": "preview",
"source": false
},
"icon": "lucide-file",
"title": "1 Task Dashboard"
}
}
]
},
{
"id": "1985378602a54327",
"type": "tabs",
"children": [
{
"id": "72a82e0b37e63751",
"type": "leaf",
"state": {
"type": "full-calendar-view",
"state": {},
"icon": "calendar-glyph",
"title": "Calendar"
}
}
]
}
],
"direction": "vertical"
},
"left": {
"id": "e5fa84f508f70d4a",
"type": "split",
"children": [
{
"id": "7f6b5f16b83d9662",
"type": "tabs",
"children": [
{
"id": "2ae31a6460a580c2",
"type": "leaf",
"state": {
"type": "file-explorer",
"state": {
"sortOrder": "alphabetical",
"autoReveal": false
},
"icon": "lucide-folder-closed",
"title": "Files"
}
},
{
"id": "5dcbb689e8ca2590",
"type": "leaf",
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"matchingCase": false,
"explainSearch": false,
"collapseAll": false,
"extraContext": false,
"sortOrder": "alphabetical"
},
"icon": "lucide-search",
"title": "Search"
}
},
{
"id": "52955ed22e885f54",
"type": "leaf",
"state": {
"type": "bookmarks",
"state": {},
"icon": "lucide-bookmark",
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8
.sessions/Digital_Control_Theory.vim
View File

@ -13,7 +13,7 @@ if &shortmess =~ 'A'
else else
set shortmess=aoO set shortmess=aoO
endif endif
badd +32 Project/Project_Proposal.md badd +65 Project/Project_Proposal.md
argglobal argglobal
%argdel %argdel
edit Project/Project_Proposal.md edit Project/Project_Proposal.md
@ -31,12 +31,12 @@ silent! normal! zE
let &fdl = &fdl let &fdl = &fdl
32 32
normal! zo normal! zo
let s:l = 32 - ((17 * winheight(0) + 27) / 55) let s:l = 65 - ((54 * winheight(0) + 33) / 67)
if s:l < 1 | let s:l = 1 | endif if s:l < 1 | let s:l = 1 | endif
keepjumps exe s:l keepjumps exe s:l
normal! zt normal! zt
keepjumps 32 keepjumps 65
normal! 0 normal! 057|
tabnext 1 tabnext 1
if exists('s:wipebuf') && len(win_findbuf(s:wipebuf)) == 0 && getbufvar(s:wipebuf, '&buftype') isnot# 'terminal' if exists('s:wipebuf') && len(win_findbuf(s:wipebuf)) == 0 && getbufvar(s:wipebuf, '&buftype') isnot# 'terminal'
silent exe 'bwipe ' . s:wipebuf silent exe 'bwipe ' . s:wipebuf

10
.sessions/Sensor_Research.vim
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@ -13,13 +13,11 @@ if &shortmess =~ 'A'
else else
set shortmess=aoO set shortmess=aoO
endif endif
badd +74 3-99\ Research/Sensors/Handbook\ of\ Modern\ Sensors/Chapter\ 4\ -\ Interface\ Electronic\ Circuits.md badd +19 3-99\ Research/Sensors/Handbook\ of\ Modern\ Sensors/Chapter\ 4\ -\ Interface\ Electronic\ Circuits.md
badd +7 .sessions/nvim_config.vim
argglobal argglobal
%argdel %argdel
edit .sessions/nvim_config.vim edit 3-99\ Research/Sensors/Handbook\ of\ Modern\ Sensors/Chapter\ 4\ -\ Interface\ Electronic\ Circuits.md
argglobal argglobal
balt 3-99\ Research/Sensors/Handbook\ of\ Modern\ Sensors/Chapter\ 4\ -\ Interface\ Electronic\ Circuits.md
setlocal fdm=manual setlocal fdm=manual
setlocal fde=0 setlocal fde=0
setlocal fmr={{{,}}} setlocal fmr={{{,}}}
@ -30,11 +28,11 @@ setlocal fdn=20
setlocal fen setlocal fen
silent! normal! zE silent! normal! zE
let &fdl = &fdl let &fdl = &fdl
let s:l = 7 - ((6 * winheight(0) + 30) / 60) let s:l = 19 - ((0 * winheight(0) + 33) / 67)
if s:l < 1 | let s:l = 1 | endif if s:l < 1 | let s:l = 1 | endif
keepjumps exe s:l keepjumps exe s:l
normal! zt normal! zt
keepjumps 7 keepjumps 19
normal! 0 normal! 0
tabnext 1 tabnext 1
if exists('s:wipebuf') && len(win_findbuf(s:wipebuf)) == 0 && getbufvar(s:wipebuf, '&buftype') isnot# 'terminal' if exists('s:wipebuf') && len(win_findbuf(s:wipebuf)) == 0 && getbufvar(s:wipebuf, '&buftype') isnot# 'terminal'

7
300s School/ME 2046 - Digital Control Theory/Project/Project_Proposal.md
View File

@ -56,7 +56,12 @@ For this project, a simulated SAR ADC will be created. This simulated SAR ADC
will be created to mimic the register behavior of the SAR ADC found on the will be created to mimic the register behavior of the SAR ADC found on the
ATMega328P, where the data registers are updated one by one on each clock cycle, ATMega328P, where the data registers are updated one by one on each clock cycle,
and a flag register is utilized to indicate a conversion has finished. This and a flag register is utilized to indicate a conversion has finished. This
simulated SAR ADC will be paired with a simulated controller operating simulated SAR ADC will be paired with a simulated controller fast enough to
make state estimates and issue control commands between batches of ADC
bits (3-4 bits per batch). This controller will estimate the state of the system
at this partial-sample, and combined with the current ADC readout, perform control.
For a plant, I plan to use the case of a read head on a hard disk drive. Hard
disk drives require extreme precision to operate properly
*explain how SAR updates registers continuously for some devices. perhaps we can use first couple bits with a state estimator to make a guess what the final value will be and do control. then as we get mroe info, and with our model of the system, we can correct for how wrong we were* *explain how SAR updates registers continuously for some devices. perhaps we can use first couple bits with a state estimator to make a guess what the final value will be and do control. then as we get mroe info, and with our model of the system, we can correct for how wrong we were*