diff --git a/201 Metadata/My Library.bib b/201 Metadata/My Library.bib
index d90c95226..9321c3fb1 100644
--- a/201 Metadata/My Library.bib	
+++ b/201 Metadata/My Library.bib	
@@ -7601,6 +7601,26 @@ for defect classification of TFT–LCD panels.pdf}
   file = {/home/danesabo/Zotero/storage/84GMPWDD/DBN for aircraft wing health monitoring DT.pdf}
 }
 
+@article{linInnovativeSuccessiveApproximation2021,
+  title = {An {{Innovative Successive Approximation Register Analog-to-Digital Converter}} for a {{Nine-Axis Sensing System}}},
+  author = {Lin, Chih-Hsuan and Wen, Kuei-Ann},
+  date = {2021-03},
+  journaltitle = {Journal of Low Power Electronics and Applications},
+  volume = {11},
+  number = {1},
+  pages = {3},
+  publisher = {Multidisciplinary Digital Publishing Institute},
+  issn = {2079-9268},
+  doi = {10.3390/jlpea11010003},
+  url = {https://www.mdpi.com/2079-9268/11/1/3},
+  urldate = {2025-03-28},
+  abstract = {With nine-axis sensing systems in 5G smartphones, mobile power consumption has become increasingly important, and ultra-low-power (ULP) sensor circuits can decrease power consumption to tens of microwatts. This paper presents an innovative successive approximation register analog-to-digital converter, which comprises fine (three most significant bits (MSBs) plus course conversion (11 least significant bits (LSBs)) capacitive digital-to-analog converters (CDACs), ULP, four-mode reconfigurable resolution (9, 10, 11, or 12 bits), an internally generated clock, meta-detection, the switching base midpoint voltage (Vm) (SW-B-M), bit control logic, multi-phase control logic, fine (three MSBs) plus course conversion (11 LSBs) switch control logic, phase control logic, and an input signal plus negative voltage (VI + NEG) voltage generator. Then, the mechanism of the discrete Fourier transform (DFT)-based calibration is applied. The scalable voltage technique was used, and the analog/digital voltage was Vanalog (1.5 V) and Vdigital (0.9 V) to meet the specifications of the nine-axis ULP sensing system. The CDACs can reconfigure four-mode resolutions, 9–12 bits, for use in nine-axis sensor applications. The corresponding dynamic signal-to-noise and distortion ratio performance was 50.78, 58.53, 62.42, and 66.51 dB. In the 12-bit mode, the power consumption of the ADC was approximately 2.7 μW, and the corresponding figure of merit (FoM) was approximately 30.5 fJ for each conversion step.},
+  issue = {1},
+  langid = {english},
+  keywords = {DFT-based,fine (3 MSBs) plus course conversion (11 LSBs) CDAC,reconfigurable,SAR-ADC},
+  file = {/home/danesabo/Zotero/storage/DKEJCQ8S/Lin and Wen - 2021 - An Innovative Successive Approximation Register Analog-to-Digital Converter for a Nine-Axis Sensing.pdf}
+}
+
 @article{linUncertaintyQuantificationSoftware2021,
   title = {Uncertainty Quantification and Software Risk Analysis for Digital Twins in the Nearly Autonomous Management and Control Systems: {{A}} Review},
   shorttitle = {Uncertainty Quantification and Software Risk Analysis for Digital Twins in the Nearly Autonomous Management and Control Systems},